Digital VLSI Design Problems and Solution with Verilog expertly addresses fundamental concepts of digital design along with their design verification with Verilog HDL. This book provides a common source of knowledge for the beginners as well as research students working in the area of VLSI design covering digital design from switch level to FPGA based implementation using hardware description language (HDL). Comprised of eleven chapters, this book describes the fundamental concepts behind digital circuit design, including combinational and sequential circuit design fundamentals, based on Boolean algebra. This book also addresses the implementation of logic functionality of complex digital circuits with Verilog, using software simulators like ISim of Xilinx. Aimed at students, it implements logic functions using a programmable device (PLD, CPLD, FPGA) and covers real-time examples of digital circuit design using Verilog.

Suman Lata Tripathi is Professor of VLSI Design at Lovely Professional University, India. She is a senior member of the IEEE and received her PhD in microelectronics and VLSI Design from Motilal Nehru National Institute of Technology, Allahabad, India.

Sobhit Saxena is Associate Professor of VLSI Design at the Lovely Professional University in India. He received his PhD from IIT Roorkee.

Sanjeet Kumar Sinha, PhD, is Associate Professor of VLSI Design at the Lovely Professional University, India. He received his PhD from the National Institute of Technology, Silchar, India

Govind Singh Patel, PhD, is Professor of VLSI Design at the Lovely Professional University, India. He received his doctorate from Thapar University in Patiala, India.

Preface xi

About the Authors xiii

1 Combinational Circuit Design 1

1.1 Logic Gates 1

1.1.1 Universal Gate Operation 3

1.1.2 Combinational Logic Circuits 5

1.2 Combinational Logic Circuits Using MSI 6

1.2.1 Adders 6

1.2.2 Multiplexers 12

1.2.3 De-multiplexer 14

1.2.4 Decoders 15

1.2.5 Multiplier 17

1.2.6 Comparators 18

1.2.7 Code Converters 19

1.2.8 Decimal to BCD Encoder 20

Review Questions 21

Multiple Choice Questions 22

Reference 23

2 Sequential Circuit Design 25

2.1 Flip-flops (F/F) 25

2.1.1 S-R F/F 25

2.1.2 D F/F 26

2.1.3 J-K F/F 26

2.1.4 T F/F 28

2.1.5 F/F Excitation Table 29

2.1.6 F/F Characteristic Table 29

2.2 Registers 31

2.2.1 Serial I/P and Serial O/P (SISO) 31

2.2.2 Serial Input and Parallel Output (SIPO) 31

2.2.3 Parallel Input and Parallel Output (PIPO) 32

2.2.4 Parallel Input and Serial Output (PISO) 32

2.3 Counters 33

2.3.1 Synchronous Counter 33

2.3.2 Asynchronous Counter 33

2.3.3 Design of a 3-Bit Synchronous Up-counter 34

2.3.4 Ring Counter 36

2.3.5 Johnson Counter 37

2.4 Finite State Machine (FSM) 37

2.4.1 Mealy and Moore Machine 38

2.4.2 Pattern or Sequence Detector 38

Review Questions 41

Multiple Choice Questions 41

Reference 42

3 Introduction to Verilog HDL 43

3.1 Basics of Verilog HDL 43

3.1.1 Introduction to VLSI 43

3.1.2 Analog and Digital VLSI 43

3.1.3 Machine Language and HDLs 44

3.1.4 Design Methodologies 44

3.1.5 Design Flow 45

3.2 Level of Abstractions and Modeling Concepts 45

3.2.1 Gate Level 45

3.2.2 Dataflow Level 47

3.2.3 Behavioral Level 47

3.2.4 Switch Level 47

3.3 Basics (Lexical) Conventions 47

3.3.1 Comments 47

3.3.2 Whitespace 48

3.3.3 Identifiers 48

3.3.4 Escaped Identifiers 48

3.3.5 Keywords 48

3.3.6 Strings 49

3.3.7 Operators 49

3.3.8 Numbers 49

3.4 Data Types 50

3.4.1 Values 50

3.4.2 Nets 50

3.4.3 Registers 51

3.4.4 Vectors 51

3.4.5 Integer Data Type 51

3.4.6 Real Data Type 51

3.4.7 Time Data Type 52

3.4.8 Arrays 52

3.4.9 Memories 52

3.5 Testbench Concept 53

Multiple Choice Questions 53

References 54

4 Programming Techniques in Verilog I 55

4.1 Programming Techniques in Verilog I 55

4.2 Gate-Level Model of Circuits 55

4.3 Combinational Circuits 57

4.3.1 Adder and Subtractor 57

4.3.2 Multiplexer and De-multiplexer 66

4.3.3 Decoder and Encoder 71

4.3.4 Comparator 75

Review Questions 77

Multiple Choice Questions 77

References 78

5 Programming Techniques in Verilog II 79

5.1 Programming Techniques in Verilog II 79

5.2 Dataflow Model of Circuits 79

5.3 Dataflow Model of Combinational Circuits 80

5.3.1 Adder and Subtractor 80

5.3.2 Multiplexer 82

5.3.3 Decoder 85

5.3.4 Comparator 86

5.4 Testbench 87

5.4.1 Dataflow Model of the Half Adder and Testbench 88

5.4.2 Dataflow Model of the Half Subtractor and Testbench 89

5.4.3 Dataflow Model of 2 × 1 Mux and Testbench 90

5.4.4 Dataflow Model of 4 × 1 Mux and Testbench 91

5.4.5 Dataflow Model of 2-to-4 Decoder and Testbench 92

Review Questions 93

Multiple Choice Questions 94

References 95

6 Programming Techniques in Verilog II 97

6.1 Programming Techniques in Verilog II 97

6.2 Behavioral Model of Combinational Circuits 98

6.2.1 Behavioral Code of a Half Adder Using If-else 98

6.2.2 Behavioral Code of a Full Adder Using Half Adders 99

6.2.3 Behavioral Code of a 4-bit Full Adder (FA) 100

6.2.4 Behavioral Model of Multiplexer Circuits 101

6.2.5 Behavioral Model of a 2-to-4 Decoder 104

6.2.6 Behavioral Model of a 4-to-2 Encoder 106

6.3 Behavioral Model of Sequential Circuits 108

6.3.1 Behavioral Modeling of the D-Latch 108

6.3.2 Behavioral Modeling of the D-F/F 109

6.3.3 Behavioral Modeling of the J-K F/F 110

6.3.4 Behavioral Modeling of the D-F/F Using J-K F/F 112

6.3.5 Behavioral Modeling of the T-F/F Using J-K F/F 113

6.3.6 Behavior Modeling of an S-R F/F Using J-K F/F 114

Review Questions 115

Multiple Choice Questions 115

References 116

7 Digital Design Using Switches 117

7.1 Switch-Level Model 117

7.2 Digital Design Using CMOS Technology 118

7.3 CMOS Inverter 119

7.4 Design and Implementation of the Combinational Circuit Using Switches 120

7.4.1 Types of Switches 120

7.4.2 CMOS Switches 121

7.4.3 Resistive Switches 121

7.4.4 Bidirectional Switches 122

7.4.5 Supply and Ground Requirements 122

7.5 Logic Implementation Using Switches 123

7.5.1 Digital Design with a Transmission Gate 127

7.6 Implementation with Bidirectional Switches 127

7.6.1 Multiplexer Using Switches 127

7.7 Verilog Switch-Level Description with Structural-Level Modeling 131

7.8 Delay Model with Switches 131

Review Questions 132

Multiple Choice Questions 133

References 134

8 Advance Verilog Topics 135

8.1 Delay Modeling and Programming 135

8.1.1 Delay Modeling 135

8.1.2 Distributed-Delay Model 135

8.1.3 Lumped-Delay Model 136

8.1.4 Pin-to-Pin-Delay Model 137

8.2 User-Defined Primitive (UDP) 138

8.2.1 Combinational UDPs 139

8.2.2 Sequential UDPs 142

8.2.3 Shorthands in UDP 144

8.3 Task and Function 144

8.3.1 Difference between Task and Function 144

8.3.2 Syntax of Task and Function Declaration 145

8.3.3 Invoking Task and Function 147

8.3.4 Examples of Task Declaration and Invocation 147

8.3.5 Examples of Function Declaration and Invocation 148

Review Questions 148

Multiple Choice Questions 149

References 149

9 Programmable and Reconfigurable Devices 151

9.1 Logic Synthesis 151

9.1.1 Technology Mapping 151

9.1.2 Technology Libraries 152

9.2 Introduction of a Programmable Logic Device 152

9.2.1 PROM, PAL and PLA 153

9.2.2 SPLD and CPLD 154

9.3 Field-Programmable Gate Array 156

9.3.1 FPGA Architecture 158

9.4 Shannon’s Expansion and Look-up Table 158

9.4.1 2-Input LUT 159

9.4.2 3-Input LUT 160

9.5 FPGA Families 161

9.6 Programming with FPGA 161

9.6.1 Introduction to Xilinx Vivado Design Suite for FPGA-Based Implementations 163

9.7 ASIC and Its Applications 163

Review Questions 164

Multiple Choice Questions 164

References 167

10 Project Based on Verilog HDLs 169

10.1 Project Based on Combinational Circuit Design Using Verilog HDL 171

10.1.1 Full Adder Using Switches at Structural Level Model 171

10.1.2 Ripple-Carry Full Adder (RCFA) 174

10.1.3 4-bit Carry Look-ahead Adder (CLA) 174

10.1.4 Design of a 4-bit Carry Save Adder (CSA) 176

10.1.5 2-bit Array Multiplier 177

10.1.6 2 × 2 Bit Division Circuit Design 178

10.1.7 2-bit Comparator 179

10.1.8 16-bit Arithmetic Logic Unit 180

10.1.9 Design and Implementation of 4 × 16 Decoder Using 2 × 4 Decoder 181

10.2 Project Based on Sequential Circuit Design Using Verilog HDL 182

10.2.1 Design of 4-bit Up/down Counter 182

10.2.2 LFSR Based 8-bit Test Pattern Generator 183

10.3 Counter Design 185

10.3.1 Random Counter that Counts Sequence like 2,4,6,8,2,8…and so On 185

10.3.2 Use of Task at the Behavioral-Level Model 187

10.3.3 Traffic Signal Light Controller 188

10.3.4 Hamming Code(h,k) Encoder/Decoder 189

Review Questions 192

Multiple Choice Questions 192

References 193

11 System Verilog 195

11.1 Introduction 195

11.2 Distinct Features of System Verilog 195

11.2.1 Data Types 196

11.2.2 Arrays 197

11.2.3 Typedef 199

11.2.4 Enum 200

11.3 Always_type 201

11.4 $log2c() Function 202

11.5 System-Verilog as a Verification Language 203

Review Questions 203

Multiple Choice Questions 204

Reference 204

Index 205