Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal Vlsi Circuits,9780792379911

Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal Vlsi Circuits

by ;
ISBN13: 9780792379911
ISBN10: 0792379918
Format: Hardcover
Pub. Date: 2000-09-01
Publisher(s): Kluwer Academic Pub
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Summary

Today's electronic design and test engineers deal with several types of subsystems, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods. This book provides a careful selection of essential topics on all three types of circuits. The outcome of testing is product quality, which means 'meeting the user's needs at a minimum cost.' The book includes test economics and techniques for determining the defect level of VLSI chips. Besides being a textbook for a course on testing, it is a complete testability guide for an engineer working on any kind of electronic device or system or a system-on-a-chip. The book consists of: Part I: Introduction, Test Process and ATE, Test Economics and Product Quality, Fault Modeling; Part II: Logic and Fault Simulation, Testability Measures, Combinatorial ATPG, Sequential ATPG, Memory Test, DSP-Based Analog Test, Model-Based Analog Test, Delay Test, IDDQ Test; Part III: DFT and Scan Design, BIST, Boundary Scan, Analog Test Bus, System Test and Core-Based Design, Future Testing; Appendices: Cyclic Redundancy Code Theory, Primitive Polynomials, Books on Testing; Bibliography: over 700 entries.

Table of Contents

Preface xv
About The Authors xvii
I INTRODUCTION TO TESTING 1(80)
Introduction
3(14)
Testing Philosophy
4(2)
Role of Testing
6(1)
Digital and Analog VLSI Testing
7(2)
VLSI Technology Trends Affecting Testing
9(6)
Scope of this Book
15(2)
VLSI Testing Process And Test Equipment
17(18)
How to Test Chips?
18(6)
Types of Testing
18(6)
Automatic Test Equipment
24(6)
Advantest Model T6682 ATE
24(4)
LTX Fusion ATE
28(1)
Multi-Site Testing
29(1)
Electrical Parametric Testing
30(4)
Summary
34(1)
Test Economics And Product Quality
35(22)
Test Economics
36(8)
Defining Costs
36(2)
Production
38(3)
Benefit-Cost Analysis
41(1)
Economics of Testable Design
42(2)
The Rule of Ten
44(1)
Yield
44(3)
Defect Level as a Quality Measure
47(6)
Test Data Analysis
48(2)
Defect Level Estimation
50(3)
Summary
53(4)
Fault Modeling
57(24)
Defects, Errors, and Faults
57(2)
Functional Versus Structural Testing
59(1)
Levels of Fault Models
60(1)
A Glossary of Fault Models
60(10)
Single Stuck-at Fault
70(11)
Fault Equivalence
72(1)
Equivalence of Single Stuck-at Faults
73(1)
Fault Collapsing
74(1)
Fault Dominance and Checkpoint Theorem
75(3)
Summary
78(3)
II TEST METHODS 81(382)
Logic And Fault Simulation
83(46)
Simulation for Design Verification
83(5)
Simulation for Test Evaluation
88(3)
Modeling Circuits for Simulation
91(10)
Modeling Levels and Types of Simulators
91(2)
Hierarchical Connectivity Description
93(1)
Gate-level Modeling of MOS Networks
94(2)
Modeling Signal States
96(2)
Timing
98(3)
Algorithms for True-Value Simulation
101(4)
Compiled-Code Simulation
102(1)
Event-Driven Simulation
103(2)
Algorithms for Fault Simulation
105(15)
Serial Fault Simulation
106(1)
Parallel Fault Simulation
107(2)
Deductive Fault Simulation
109(4)
Concurrent Fault Simulation
113(3)
Roth's TEST-DETECT Algorithm
116(1)
Differential Fault Simulation
117(3)
Statistical Methods for Fault Simulation
120(5)
Fault Sampling
121(4)
Summary
125(4)
Testability Measures
129(26)
SCOAP Controllability and Observability
131(17)
Combinational SCOAP Measures
132(2)
Combinational Circuit Example
134(6)
Sequential SCOAP Measures
140(2)
Sequential Circuit Example
142(6)
High-Level Testability Measures
148(2)
Summary
150(5)
Combinational Circuit Test Generation
155(56)
Algorithms and Representations
156(12)
Structural vs. Functional Test
156(1)
Definition of Automatic Test-Pattern Generator
157(1)
Search Space Abstractions
158(1)
Algorithm Completeness
159(1)
ATPG Algebras
159(1)
Algorithm Types
160(8)
Redundancy Identification (RID)
168(4)
Testing as a Global Problem
172(1)
Definitions
172(4)
Significant Combinational ATPG Algorithms
176(28)
D-Calculus and D-Algorithm (Roth)
176(10)
PODEM (Goel)
186(6)
FAN (Fujiwara and Shimino)
192(5)
Advanced Algorithms
197(7)
Test Generation Systems
204(1)
Test Compaction
205(1)
Summary
206(5)
Sequential Circuit Test Generation
211(42)
ATPG for Single-Clock Synchronous Circuits
212(2)
A Simplified Problem
214(1)
Time-Frame Expansion Method
214(24)
Use of Nine-Valued Logic
216(2)
Development of Time-Frame Expansion Methods
218(4)
Approximate Methods
222(1)
Implementation of Time-Frame Expansion Methods
222(3)
Complexity of Sequential ATPG
225(1)
Cycle-Free Circuits
225(4)
Cyclic Circuits
229(2)
Clock Faults and Multiple-Clock Circuits
231(1)
Asynchronous Circuits
232(6)
Simulation-Based Sequential Circuit ATPG
238(10)
CONTEST Algorithm
239(7)
Genetic Algorithms
246(2)
Summary
248(5)
Memory Test
253(56)
Memory Density and Defect Trends
255(3)
Notation
258(1)
Faults
259(2)
Fault Manifestations
259(1)
Failure Mechanisms
260(1)
Memory Test Levels
261(1)
March Test Notation
262(1)
Fault Modeling
263(21)
Diagnosis Versus Testing Needs
265(1)
Reduced Functional Faults
266(10)
Relation Between Fault Models and Physical Defects
276(2)
Multiple Fault Models
278(3)
Frequency of Faults
281(3)
Memory Testing
284(22)
Functional RAM Testing with March Tests
284(2)
Testing RAM Neighborhood Pattern-Sensitive Faults
286(8)
Testing RAM Technology and Layout-Related Faults
294(1)
RAM Test Hierarchy
295(1)
Cache RAM Chip Testing
296(4)
Functional ROM Chip Testing
300(1)
Electrical Parametric Testing
301(5)
Summary
306(3)
DSP-Based Analog And Mixed-Signal Test
309(76)
Analog and Mixed-Signal Circuit Trends
309(5)
Definitions
314(3)
Functional DSP-Based Testing
317(5)
Concept
317(2)
Mechanism of DSP-Based Testers
319(1)
Waveform Synthesis
320(2)
Waveform Sampling and Digitization
322(1)
Static ADC and DAC Testing Methods
322(13)
Transmission vs. Intrinsic Parameters
323(2)
Uncertainty and Distortion in Ideal ADCs
325(1)
DAC Transfer Function Error
325(1)
ADC Transfer Function Error
326(1)
Flash ADC Testing Methods
327(5)
DAC Testing Methods
332(3)
Realizing Emulated Instruments Using Fourier Transforms
335(31)
Fourier Voltmeter
345(5)
Testing of Analog Devices Using Non-Coherent Sampling
350(6)
Coherent Multi-Tone Testing
356(8)
ATE Vector Operations
364(2)
CODEC Testing
366(10)
Considerations for CODEC Performance Tests
369(3)
CODEC Tests
372(4)
Dynamic Flash ADC Testing FFT Technique
376(1)
Advanced Topics
377(5)
Event Digitization
377(3)
Measuring Random Noise
380(2)
Summary
382(3)
Model-Based Analog And Mixed-Signal Test
385(32)
Analog Testing Difficulties
386(1)
Analog Fault Models
387(2)
Levels of Abstraction
389(1)
Types of Analog Testing
389(1)
Analog Fault Simulation
390(7)
Motivation
391(1)
DC Fault Simulation of Nonlinear Circuits
391(4)
Linear Analog Circuit AC Fault Simulation
395(2)
Monte-Carlo Simulation
397(1)
Analog Automatic Test-Pattern Generation
397(16)
ATPG Using Sensitivities
398(8)
ATPG Using Signal Flow Graphs
406(7)
Additional Methods
413(1)
Summary
413(4)
Delay Test
417(22)
Delay Test Problem
417(3)
Path-Delay Test
420(8)
Test Generation for Combinational Circuits
424(3)
Number of Paths in a Circuit
427(1)
Transition Faults
428(1)
Delay Test Methodologies
429(5)
Slow-Clock Combinational Test
429(1)
Enhanced-Scan Test
430(1)
Normal-Scan Sequential Test
431(1)
Variable-Clock Non-Scan Sequential Test
432(2)
Rated-Clock Non-Scan Sequential Test
434(1)
Practical Considerations in Delay Testing
434(2)
At-Speed Testing
435(1)
Summary
436(3)
IDDQ Test
439(24)
Motivation
439(2)
Faults Detected by IDDQ Tests
441(5)
IDDQ Testing Methods
446(7)
IDDQ Fault Coverage Metrics
446(2)
IDDQ Test Vector Selection from Stuck-Fault Vector Sets
448(3)
Instrumentation Problems
451(1)
Current Limit Setting
452(1)
Surveys of IDDQ Testing Effectiveness
453(2)
Limitations of IDDQ Testing
455(1)
Delta IDDQ Testing
456(2)
IDDQ Built-In Current Testing
458(2)
IDDQ Design for Testability
460(1)
Summary
460(3)
III DESIGN FOR TESTABILITY 463(152)
Digital DFT And Scan Design
465(24)
Ad-Hoc DFT Methods
466(1)
Scan Design
467(12)
Scan Design Rules
469(2)
Tests for Scan Circuits
471(3)
Multiple Scan Registers
474(1)
Overheads of Scan Design
474(3)
Design Automation
477(2)
Physical Design and Timing Verification of Scan
479(1)
Partial-Scan Design
479(4)
Variations of Scan
483(2)
Summary
485(4)
Built-In Self-Test
489(60)
The Economic Case for BIST
490(5)
Chip/board Area Cost vs. Tester Cost
492(2)
Chip/Board Area Cost vs. System Downtime Cost
494(1)
Random Logic BIST
495(34)
Definitions
495(1)
BIST Process
496(2)
BIST Pattern Generation
498(14)
BIST Response Compaction
512(7)
Built-In Logic Block Observers
519(2)
Test-Per-Clock BIST Systems
521(1)
Test-Per-Scan BIST Systems
521(4)
Circular Self-Test Path System
525(1)
Circuit Initialization
526(1)
Device Level BIST
526(2)
Test Point Insertion
528(1)
Memory BIST
529(11)
Definitions
530(2)
March Test SRAM BIST
532(2)
SRAM BIST with MISR
534(2)
Neighborhood Pattern Sensitive Fault Test DRAM BIST
536(3)
Transparent Memory BIST Tests
539(1)
Complex Examples
539(1)
Delay Fault BIST
540(3)
Summary
543(6)
Boundary Scan Standard
549(26)
Motivation
550(3)
Purpose of Standard
552(1)
System Configuration with Boundary Scan
553(16)
TAP Controller and Port
553(4)
Boundary Scan Test Instructions
557(7)
Pin Constraints of the Standard
564(5)
Boundary Scan Description Language
569(3)
BSDL Description Components
570(1)
Pin Descriptions
571(1)
Summary
572(3)
Analog Test Bus Standard
575(20)
Analog Circuit Design for Testability
576(1)
Analog Test Bus (ATB)
576(15)
Targeted Analog Faults
577(2)
Analog Test Access Port (ATAP)
579(1)
Test Bus Interface Circuit (TBIC)
580(3)
Analog Boundary Module (ABM)
583(2)
Instructions for 1149.4 Standard
585(4)
Other 1149.4 Standard Features
589(2)
Summary
591(4)
System Test And Core-Based Design
595(18)
System Test Problem Defined
596(1)
Functional Test
597(1)
Microprocessor Test
598(1)
Diagnostic Test
598(6)
Fault Dictionary
599(1)
Diagnostic Tree
600(2)
A System Test Example
602(2)
Testable System Design
604(2)
Core-Based Design and Test-Wrapper
606(1)
A Test Architecture for System-on-a-Chip (SOC)
607(1)
An Integrated Design and Test Approach
608(2)
Summary
610(3)
The Future of Testing
613(2)
A CYCLIC REDUNDANCY CODE THEORY 615(4)
Polynomial Multiplier
616(1)
Polynomial Divider
617(2)
B PRIMITIVE POLYNOMIALS OF DEGREE 1 TO 100 619(2)
C BOOKS ON TESTING 621(10)
General and Tutorial
621(1)
Analog and Mixed-Signal Circuit Test
622(1)
ATE, Test Programming, and Production Test
622(1)
Board and MCM Test and Boundary Scan
623(1)
Built-In Self-Test
624(1)
Delay Fault Test
624(1)
Design for Testability
624(1)
Fault Modeling
625(1)
Fault Tolerance and Diagnosis
625(1)
Formal Verification
625(1)
High-Level Test and Verification
626(1)
IDDQ Test
626(1)
Memory Test
626(1)
Microprocessor Verification and Test
627(1)
Semiconductor Defect Mechanisms
627(1)
System Test
627(1)
Test Economics
627(1)
Test Evaluation
628(1)
Test Generation
628(1)
Periodicals
628(1)
Conferences and Workshops
629(1)
Web Sites
629(2)
Bibliography 631(40)
Index 671

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